1. Field of the Invention
The present invention relates generally to a semiconductor memory device, and more particularly to improvements on a memory cell array in a mask ROM.
2. Description of the Background Art
Memory ICs in wide use today can be largely classified into an RWM (Read Write Memory) to and from which writing and reading can be performed after its fabrication, and an ROM (Read Only Memory) used exclusively for reading to which writing is not possible after its fabrication. Among the two types, the ROM memory is used for storing fixed information such as character patterns, etc. because stored information is not erased when power is off. The ROMs further include an EPROM (Erasable and Programmable ROM) capable of changing stored information electrically after its fabrication, and capable of erasing stored information by radiation of ultra violet rays, etc., and a mask ROM which information is written in at the time of manufacturing and the stored information can not be changed. The mask ROM is often used for storing fixed data such as character patterns for a CRT display and BASIC programs for a personal computer.
The memory part of a mask ROM commercially available at present generally includes a plurality of MOS transistors arranged in a matrix. The MOS transistor is used as a memory cell. Three areas for source, drain and gate are necessary when an MOS transistor is formed on a semiconductor substrate. The size of each of these three regions must be sufficient for achieving functions as an MOS transistor, and therefore can not be reduced limitlessly. When the MOS transistor is used as a memory cell, miniaturization of the entire area occupied by the memory naturally has its limit, and, therefore, recent demands for miniaturization of semiconductor integrated circuit devices can not be satisfied. Especially as the storage capacity of a mask ROM increases, the more serious will be this problem of meeting the demands. Meanwhile, demands for the larger storage capacities of memory ICs including the mask ROM have been even more prevalent in recent years.
Use of a mask ROM using elements of diode structure in place of elements of MOS structure is proposed for solving the above-mentioned problem (see, for example, Japanese Patent Publication No. 61-1904, and Japanese Patent Laying-Open No. 63-137471).
FIGS. 3A to 3C are schematic views each showing a structure of a memory cell array of an improved mask ROM shown in Japanese Patent Publication No. 61-1904. FIG. 3A is a plan view, FIGS. 3B and 3C are sectional views of the memory cell array shown in FIG. 3A taken along dotted lines A and B, respectively. Referring to these figures, the memory cell array is formed on a semiconductor substrate of monocrystalline silicon 40. The substrate 40 has on its surface an insulating film (not shown) formed of a silicon oxide film. A plurality of strip shaped N type polysilicon layers 42 are provided in parallel to each other on the substrate. An insulating layer 41 is formed entirely on the semiconductor substrate 40 including the polysilicon layers 42. The insulating layer 41 is selectively provided with openings, i.e. contact holes 44. By introducing an impurity into the polysilicon layer 42 under the contact holes, P type polysilicon regions 45 are formed. A plurality of strip shaped conductive layers 43 parallel to each other are provided on the insulating film 41 and the contact holes 44 crossing the polysilicon layers 42. The contact holes 44 are selectively provided at the crossing points of the polysilicon layers 42 and the conductive layers 43. The strip shaped polysilicon layers 42 each correspond to word lines different from each other, and the strip shaped conductive layers 43 each correspond to bit lines different from each other.
As can be seen from FIG. 3A, the crossing points of the plurality of strip shaped polysilicon layers 42 and the plurality of strip shaped conductive layers 43 constitute a matrix. Referring to FIGS. 3B and 3C, among these crossing points, PN junctions are formed in the polysilicon layers 42 under the contact holes 44, only in the ones provided with the contact holes 44. If forward voltage is applied to the conductive layer 43 at the crossing point provided with the contact hole 44, current flows through the polysilicon layer 42. On the other hand, if forward voltage is applied to the conductive layer 43 at the crossing point without the contact hole 44, current does not flow through the polysilicon layer 42, because the conductive layer 43 and the polysilicon layer 42 are insulated by the insulating layer 42. By applying a prescribed voltage to a selected bit line and determining the presence or absence of current flowing through a selected word line, it can be determined whether the contact hole is provided at the crossing point of the conductive layer 43 corresponding to the selected bit line and the polysilicon layer 42 corresponding to the selected word line. It is therefore possible to read stored information from a mask ROM after it is manufactured as practiced conventionally, if the memory cell array of the mask ROM is manufactured by making logical values "1" and "0" correspond to the presence and absence of the contact hole and by determining the formation pattern of the contact hole depending upon information to be stored in the mask ROM. In other words, one MOS transistor is not used as one memory cell as conventionally practiced, but simply one PN junction, i.e. one diode is utilized. An area necessary for one memory cell is therefore determined by the widths of the conductive layer 43 and the polysilicon layer 42. The minimum values for the widths of the conductive layer 43 and the polysilicon layer 42 are determined by the minimum values for a line and a space in manufacturing technology available today. Reducing these widths therefore permits the area occupied by one memory cell on the substrate to be far reduced compared to conventional ones. A mask ROM having integration density far higher than in the conventional case in which an MOS transistor is used as a memory.
In the mask ROM shown in Japanese Patent Laying-Open No. 63-137471, as shown in FIG. 5, a plurality of P type diffusion layers 51 are formed parallel to each other on an N type monocrystalline silicon substrate 50. Formed on the P type diffusion layer 51 are a plurality of N type polycrystalline silicon layers 52 parallel to each other with an insulating film therebetween, and in the direction orthogonal to the P type diffusion layer 51. Contact holes are selectively formed at the crossing points of the P type diffusion layers 51 and the N type polycrystalline silicon layers 52 at that time. The P type diffusion layers 51 and the N type polycrystalline silicon layers 52 come into contact at the crossing points provided with the contact holes, thereby forming PN junctions. The presence and absence of the PN junction determines conduction and non conduction between the P type diffusion layer 51 and the N type polycrystalline silicon layer 52, so that desired information is stored in the memory cell array.
In the conventional semiconductor memory device as described above, memory cells are arranged two-dimensionally, thereby limiting high density integration. Three-dimensional arrangement of memory cells is considered for higher integration density.
In a mask ROM using an MOS transistor as a memory cell, however, the MOS transistor includes a semiconductor substrate as a part thereof, and therefore it is not possible to build them upon each other to form a multilayered structure. Similarly, the mask ROM shown in FIG. 5 using a diode element as a memory cell uses the semiconductor substrate as a part of the memory cell, i.e. the P type diffusion layer 51 is formed by introducing a P type impurity into the silicon substrate 1, so that it was not possible to build them upon each other to make a multilayered structure.
Meanwhile, in the mask ROM shown in FIGS. 3A to 3C, the semiconductor substrate is not used as a part of the memory cell, it is possible to construct a multilayered memory cell array. In the following, a manufacturing method conceivable when multilayering the mask ROM shown in FIGS. 3A to 3C will be described in conjunction with FIGS. 4A to 4C.
An insulating film 41' is formed entirely on a mask ROM shown in FIG. 4A in which one layer of memory cell is formed. Then, the insulating film 40' is selectively provided with contact holes 44'. A plurality of strip shaped polysilicon layers 46 are formed in parallel to each other and in the direction orthogonal to the conductive layer 43 on the insulating film 41' including the contact holes 44'. A P type impurity is implanted into the contact holes 44' for forming PN junctions. A multilayered structure of mask ROMs shown in FIG. 4B is provided by these manufacturing steps.
Now, an N type impurity is implanted entirely on the mask ROM shown in FIG. 4B, and the upper portions of the polysilicon layer 46 and the polysilicon layer 45' are turned into N type. Thus, an N type polysilicon layer 42' having a different conductivity type from the word line is formed (see FIG. 4C).
The following problems are observed in a thus obtained mask ROM of multilayer structure.
When the P type polysilicon layer 45' is formed, ion implantation should be performed more deeply than the polysilicon layer 46 which is later to be the word line, and, therefore the word line is greatly damaged by the ion implantation.
Further, as can be seem from FIG. 4C, the shape of impurity a of the lower N type polysilicon layer 42 is totally different from the shape of impurity b of the upper N type polysilicon layer 42', resulting in a big difference in resistance between the upper and lower word lines. This may cause variation in accessing speed, and may prevent high speed accessing.